The present invention relates to a semiconductor memory device and, more particularly, to a configuration of a static semiconductor memory device capable of stably reading data.
The term “MOS” originally stands for Metal-Oxide-Semiconductor as a stack structure. However, particularly in a field effect transistor having a MOS structure (hereinbelow, simply called “MOS transistor”), materials of a gate insulating film and a gate electrode are improved from the viewpoint of improvement in integration and manufacturing process in recent years.
For example, in a MOS transistor, from the viewpoint of, mainly, forming a source and a drain in a self-aligning manner, polysilicon is employed in place of a metal as the material of the gate electrode. From the viewpoint of improving the electric characteristic, a material having high dielectric constant is employed as the material of the gate insulating film. The material is not always limited to an oxide.
Therefore, the term “MOS” is not always limited to the stack structure of metal/oxide/semiconductor. In the specification as well, such limitation is not the precondition. That is, in view of the technical common sense, the term “MOS” means not only the abbreviation of metal/oxide/semiconductor but also includes a stack structure of conductor/insulator/semiconductor in a broad sense. Therefore, in the specification, the term “MOS transistor” refers to an insulated gate field effect transistor in which a gate electrode and a source/a drain are electrically (galvanically) isolated from each other.
As a transistor element is becoming finer, the influence of fluctuation in manufacture parameters increases, variations in the threshold voltage of a MOS transistor as a component of a memory cell become large, and the operation margin decreases. As a result, in a semiconductor memory device in low-voltage operation, it becomes difficult to read data stably.
A configuration directed to assure stable data reading operation also under such operating conditions is proposed.
In patent document 1 (Japanese Unexamined Patent Publication No. 2005-38557), a level shifter is used for a word line driver to drive a word line at a voltage level lower than that of a power supply voltage of a memory cell, thereby assuring a margin at the time of reading.